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lp62s16128b - t series 128k x 16 bit low voltage cmos sram (august, 2001, version 1.0) 1 amic technology, inc. features n operating voltage: 2.7v to 3.6v n access times: 55/70 ns (max.) n current: very low power version: operating: 55ns 40ma (max.) 70ns 35ma (max.) standby: 10 m a (max.) n full static operation, no clock or refreshing required n all inputs and outputs are directly ttl - compatible n common i/o using three - state output n data retention voltage: 2v (min.) n available in 44 - pin tsop and 48 - ball csp (6 x 8 mm) packages general description the lp62s16128b - t is a low operating current 2,097,152 - bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 2.7v to 3.6v. it is built using amic's high performance cmos process. inputs and three - state outputs are ttl compatible and allow for direct interfacing with common system bus structures. the chip enable input is provided for power - down, device enable. two byte enable inputs and an output enable input are included for easy interfacing. data reten tion is guaranteed at a power supply voltage as low as 2v. pin configurations n n tsop n n csp (chip size package) 48 - pin top view i/o 9 i/o 10 gnd vcc i/o 15 i/o 16 nc a8 nc a9 a12 a10 a11 nc a13 a14 a15 i/o 8 i/o 7 i/o 3 i/o 1 gnd vcc a0 a3 a5 a6 a4 a1 a2 nc 6 5 4 3 2 1 a b c d e f g h i/o 14 i/o 13 i/o 12 i/o 11 nc nc a7 a16 i/o 2 i/o 4 i/o 5 i/o 6 lb hb we oe ce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a3 a2 a1 a0 ce i/o 1 i/o 2 i/o 3 i/o 4 vcc gnd i/o 5 i/o 6 i/o 7 i/o 8 we a16 a15 a14 a13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a11 a10 a9 a8 nc i/o 9 i/o 10 i/o 11 i/o 12 vcc gnd i/o 13 i/o 14 i/o 15 i/o 16 lb hb oe a7 a6 lp62s16128bv-t a12 a5 a4 nc
lp62s16128b - t series (august, 2001, version 1.0) 2 amic t echnology, inc. block diagram decoder 512 x 4096 memory array column i/o input data circuit control circuit vcc gnd i/o 8 i/o 1 a16 a15 a0 we hb input data circuit i/o 9 i/o 16 lb oe ce pin descriptions -- tsop pin no. symbol descr iption 1 - 5, 18 ? 22, 24 ? 27, 42 - 44 a0 - a16 address inputs 6 ce chip enable input 7 - 10, 13 - 16, 29 - 32, 35 - 38 i/o 1 - i/o 16 data inputs/outputs 17 we write enable input 39 lb lo wer byte enable input (i/o 1 to i/o 8 ) 40 hb higher byte enable input (i/o 9 to i/o 16 ) 41 oe output enable input 11, 33 vcc power 12, 34 gnd ground 23, 28 nc no connection
lp62s16128b - t series (august, 2001, version 1.0) 3 amic t echnology, inc. pin description - csp symbol descript ion symbol description a0 - a16 address inputs hb higher byte enable input (i/o 9 - i/o 16 ) ce chip enable oe output enable i/o 1 - i/o 16 data input/output vcc power supply we write enable input gnd ground lb byte enable input (i/o 1 - i/o 8 ) nc no connection recommended dc operating conditions (t a = - 25 c to + 85 c) symbol parameter min. typ. max. unit vcc supply voltage 2.7 3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.2 - vcc + 0.3 v v il input low voltage - 0.3 - +0.6 v c l output load - - 30 pf ttl output load - - 1 -
lp62s16128b - t series (august, 2001, version 1.0) 4 amic t echnology, inc. absolute maximum ratings* vcc to gnd ................................ ............... - 0.5v to +4.6v in, in/out volt to gnd .................... - 0.5v to vcc + 0.5v operating temperatur e, topr .................... - 25 c to +85 c storage temperature, tstg ...................... - 55 c to +125 c power dissipation, p t ................................ ............... 0.7w *comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to this device. these are stress ratings only. functional oper ation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability . dc electrical characteristics (t a = - 25 c to + 85 c, vcc = 2.7v to 3.6v, gnd = 0v) symbol parameter lp62s16128b - 55llt lp62s16128b - 70llt unit conditions min. max. min. max. ? i li ? input leakage current - 1 - 1 m a v in = gnd to vcc ? i lo ? output leakage current - 1 - 1 m a ce = v ih or lb = hb = v ih v i/o = gnd to vcc i cc active power supply current - 5 - 5 ma ce = v il , lb = v il or hb = v il , i i/o = 0 ma i cc1 dynamic operating - 40 - 35 ma min. cycle, duty = 100% ce = v il , lb = v il or hb = v il , i i/o = 0 ma i cc2 current - 15 - 15 ma ce 0.2v , lb 0.2v or hb 0.2v, f = 1mhz , i i/o = 0 ma i sb - 0.5 - 0.5 ma ce = v ih or lb = hb = v ih i sb1 standby power supply current - 10 - 10 m a ce 3 vcc ? 0.2v or lb = hb 3 vcc ? 0.2v, v in 3 vcc ? 0.2v or v in 0.2v v ol output low voltage - 0.4 - 0.4 v i ol = 2.1 ma v oh output high voltage 2.2 - 2.2 - v i oh = - 1.0 ma
lp62s16128b - t series (august, 2001, version 1.0) 5 amic t echnology, inc. truth table ce oe we lb hb i/o 1 to i/o 8 mode i/o 9 to i/o 16 mode vcc current h x x x x not selec ted not selected i sb1 , i sb x x x h h high - z high - z i sb1 , i sb l l read read i cc1 , i cc2 , i cc l l h l h read high - z i cc1 , i cc2 , i cc h l high - z read i cc1 , i cc2 , i cc l l write write i cc1 , i cc2 , i cc l x l l h write high - z i cc1 , i cc2 , i cc h l high - z write i cc1 , i cc2 , i cc l h h l x high - z high - z i cc1 , i cc2 , i cc l h h x l high - z high - z i cc1 , i cc2 , i cc note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 6 pf v in = 0v c i/o * input/output capacitance 8 pf v i/o = 0v * these parameters are sampled and not 100% tested.
lp62s16128b - t series (august, 2001, version 1.0) 6 amic t echnology, inc. ac characteristics (t a = - 25 c to +85 c, vcc = 2.7v to 3.6v) symbol parameter lp62s16128b - 55llt lp62s16128b - 70llt unit min. max. min. max. r ead cycle t rc read cycle time 55 - 70 - ns t aa address access time - 55 - 70 ns t ace chip enable access time - 55 - 70 ns t be byte enable access time - 55 - 70 ns t oe output enable to output valid - 30 - 35 ns t clz chip enable to output in low z 10 - 10 - ns t blz byte enable to outupt in low z 10 - 10 - ns t olz output enable to output in low z 5 - 5 - ns t chz chip disable to output in high z - 20 - 25 ns t bhz byte disable to output in high z - 20 - 25 ns t ohz output disable to output in high z - 20 - 25 ns t oh output hold from address change 5 - 5 - ns write cycle t wc write cycle time 55 - 70 - ns t cw chip enable to end of write 50 - 60 - ns t bw byte enable to end of write 50 - 60 - ns t as address setup time 0 - 0 - ns t aw address valid to end of write 50 - 60 - ns t wp write pulse width 40 - 55 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z - 25 - 25 ns t dw data to write time overlap 25 - 30 - ns t dh data hold from write time 0 - 0 - ns t ow output active from en d of write 5 - 5 - ns note: t blz , t olz, t chz , t bhz and t ohz and t whz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
lp62s16128b - t series (august, 2001, version 1.0) 7 amic t echnology, inc. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 2 (1, 2, 3) t rc t aa address t ace t chz 5 ce hb, lb t bhz 5 oe t clz 5 t be t blz 5 t oe t olz 5 t ohz 5 d out notes: 1. we is high for read cycle. 2. device is continuously enabled ce = v il , hb = v ih and, or lb = v il . 3. address valid prior to or coincident with ce and ( hb and, or lb ) transition low. 4. oe = v il . 5. transition is measured 500mv from steady state. this parame ter is sampled and not 100% tested.
lp62s16128b - t series (august, 2001, version 1.0) 8 amic t echnology, inc. timing waveforms (continued) write cycle 1 (write enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw t bw t as 1 t wp 2 t dw t dh t ow t whz 4
lp62s16128b - t series (august, 2001, version 1.0) 9 amic t echnology, inc. timing waveforms (continued) write cycle 2 (chip enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw 2 t bw t as 1 t wp t dw t dh t ow t whz 4
lp62s16128b - t series (august, 2001, version 1.0) 10 amic t echnology, inc. timing wavefo rms (continued) write cycle 3 (byte enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw t bw 2 t as 1 t wp t dw t dh t ow t whz 4 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp , t bw ) of a low ce , we and ( hb and , or lb ). 3. t wr is measured from the earliest of ce or we or ( hb and , or lb ) going high to the end of the write cycle. 4. oe level is high or low. 5. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested.
lp62s16128b - t series (august, 2001, version 1.0) 11 amic t echnology, inc. ac test conditions input pulse levels 0.4v to 2.4v input rise and fall time 5 ns input and output timing reference levels 1.5v output load see figures 1 and 2 30pf * including scope and jig. * including scope and jig. c l ttl 5pf c l ttl figure 1. output load figure 2. output load for t clz , t olz , t bhz , t blz , t chz , t ohz , t whz , and t ow data retention characteristics (t a = - 25 c to 85 c) symbol parameter min. max. unit conditions v dr vcc for data retention 2.0 3.6 v ce 3 vcc - 0.2v or lb = hb 3 vcc - 0.2v i ccdr data retention current - 3* m a vcc = 2v, ce 3 vcc - 0.2v or lb = hb 3 vcc - 0.2v v in 3 vcc - 0.2v or v in 0.2v t cdr chip disable to data retention time 0 - ns t r operation recovery time t rc - ns see retention waveform t vr vcc rising time from data retention voltage to operating voltage 5 - ms * lp62s16128b - 70llt i ccdr : max. 1 m a at t a = 0 c to + 40 c
lp62s16128b - t series (august, 2001, version 1.0) 12 amic t echnology, inc. low vcc data retention waveform vcc ce t cdr v ih 2.7v t r v ih 2.7v data retention mode v dr 3 2v ce 3 v dr - 0.2v t vr ordering information part no. access time (ns) operating current max. (ma) standby current max. ( m m a) package lp62s16128bv - 55llt 40 10 44l tsop lp62s16128bu - 55llt 55 40 10 48l csp lp62s16128bv - 70llt 70 35 10 44l tsop lp62s16128bu - 70llt 35 10 48l csp
lp62s16128b - t series (august, 2001, version 1.0) 13 amic t echnology, inc. package information tsop 44l type ii outline dimensions unit: inches/mm 44 1 d e h e 0.254 l 1 l a 1 a 2 a s b e d y l 1 c l 23 22 symbol dimension in inch dimension in mm min. nom. max. min. nom. max. a - - 0.047 - - 1.20 a 1 0.002 - - 0.05 - - a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.010 0.014 0.018 0.25 0.35 0.45 c - 0.006 - - 0.15 - d 0.721 0.725 0.729 18.3 1 18.41 18.51 e 0.396 0.400 0.404 10.06 10.16 10.26 e - 0.031 - - 0.80 - h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l 1 - 0.031 - - 0.80 - s - - 0.036 - - 0.93 y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. dimensi on d&e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash.
lp62s16128b - t series (august, 2001, version 1.0) 14 amic t echnology, inc. 48ld csp ( 6 x 8 mm ) outline dimensions unit: mm (48tfbga) a 1 a 2 a b c d e f g h top view ball#a1 corner side view c seating plane // 0.25 c a (0.36) a b c d e f g h 1 2 3 4 5 6 1 2 3 4 5 6 c 0.10 c s 0.25 s a b b (48x) bottom view ball*a1 corner e e 1 e b e d 1 d a 0.20(4x) 0.10 c dimensions in mm symbol min. nom. max. a 1.04 1.14 1.24 a 1 0.20 0.25 0.30 a 2 0.48 0.53 0.58 d 5.90 6.00 6.10 e 7.90 8.00 8.10 d 1 --- 3.75 --- e 1 --- 5.25 --- e --- 0.75 --- b 0.30 0.35 0.40 note: 1. the ball diameter, ball pitch, stand - off & package thickness are different from jedec spec mo192 (low profile bga family). 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 3. dimension b is measured at the maximum. there shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge. 4. ball pad opening of substrate is f 0.3mm (smd) suggest to design the pcb land size as f 0.3mm (nsmd)

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